Commit by delena :: r146975 /llvm/trunk/ (2 files in 2 dirs): (link)

This is the second fix related to VZEXT_MOVL node.
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]

Commit by chandlerc :: r146974 /llvm/trunk/ (3 files in 2 dirs): (link)

Begin teaching the X86 target how to efficiently codegen patterns that
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

Commit by klimek :: r146973 /llvm/trunk/ (2 files in 2 dirs): (link)

Fixes a potential compilation error.

Pulling the template implementation into the header to guarantee
that it's visible to all possible instantiations.

Commit by klimek :: r146971 /llvm/trunk/ (2 files in 2 dirs): (link)

Pulls the implementation of skip() into JSONParser.

This is the first step towards migrating more of the parser
implementation into the parser class.

Commit by klimek :: r146970 /llvm/trunk/utils/json-bench/JSONBench.cpp: (link)

Fixing option for JSON benchmark broken since the change to size_t.

Commit by klimek :: r146968 /llvm/trunk/ (2 files in 2 dirs): (link)

Addressing style issues in JSON parser.

Commit by chandlerc :: r146966 /llvm/trunk/ (16 files in 16 dirs): (link)

Fix up the CMake build for the new files added in r146960, they're
likely to stay either way that discussion ends up resolving itself.

Commit by dblaikie :: r146965 /llvm/trunk/utils/TableGen/TGValueTypes.cpp: (link)

Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean)

Commit by nadav :: r146964 /llvm/trunk/docs/ReleaseNotes.html: (link)

Add a few lines to the release notes:
1. pointer-vector
2. type legalizer changes and vector-select
3. X86 ISA changes.

Commit by dblaikie :: r146960 /llvm/trunk/ (151 files in 49 dirs): (link)

Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch

Commit by atrick :: r146951 /llvm/trunk/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll: (link)

Unit test for r146950: LSR postinc expansion, PR11571.

Commit by atrick :: r146950 /llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp: (link)

LSR: Fix another corner case in expansion of postinc users.

Fixes PR11571: Instruction does not dominate all uses

Commit by bwilson :: r146949 /llvm/trunk/ (2 files in 2 dirs): (link)

Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.

We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.

Commit by lattner :: r146940 /llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h: (link)

fix typo

Commit by djg :: r146939 /llvm/trunk/docs/ReleaseNotes.html: (link)

Add a line to ReleaseNotes for half float.

Commit by grosbach :: r146937 /llvm/trunk/ (2 files in 2 dirs): (link)

ARM assembly shifts by zero should be plain 'mov' instructions.

"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

Commit by lattner :: r146932 /llvm/trunk/ (2 files in 2 dirs): (link)

Now that PR11464 is fixed, reapply the patch to fix PR11464,
merging types by name when we can. We still don't guarantee type name linkage
but we do it when obviously the right thing to do. This makes LTO type names
easier to read, for example.

Commit by lattner :: r146929 /llvm/trunk/ (2 files in 2 dirs): (link)

fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.

Commit by lattner :: r146928 /llvm/trunk/include/llvm/ADT/SetVector.h: (link)

add a method to improve compatibility with SmallVector.

Commit by djg :: r146927 /llvm/trunk/ (8 files in 6 dirs): (link)

Add basic generic CodeGen support for half.